1. Field of Invention
The present invention relates to a non-volatile memory (NVM) device. More particularly, the present invention relates to a flash memory device structure and manufacturing method thereof.
2. Description of Related Art
Flash memory is a memory device that allows multiple data writing, reading, and erasing operations. In addition, the stored data will be retained even after power to the device is removed. With these advantages, it has been broadly applied in personal computer and electronic equipment.
A typical flash memory device has a floating gate and a control gate fabricated using doped polysilicon. The control gate is set up above the floating gate with an inter-gate dielectric layer separating the two. Furthermore, a tunneling oxide layer is also setup between the floating gate and an underlying substrate (the so-called stack gate flash memory).
To write data into the flash memory, a bias voltage is applied to the control gate and the source/drain regions so that an electric field is set up to inject electrons into the floating gate. On the other hand, to read data from the flash memory, an operating voltage is applied to the control gate. Since the entrapment of charges inside the floating gate will directly affect the opening or closing of the underlying channel, the opening or closing of the channel can be construed as a data value of xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d. Finally, to erase data from the flash memory, the relative potential between the substrate and the drain (source) region or the control gate is raised. Hence, tunneling effect can be utilized to transfer electrons from the floating gate to the substrate or drain (source) via the tunneling oxide layer (the so-called substrate erase or drain (source) side erase) or from the floating gate to the control gate via the inter-gate dielectric layer.
FIG. 1 is a schematic cross-sectional view of the stack gate structure of a conventional flash memory (according to U.S. Pat. No. 6,214,668). As shown in FIG. 1, the flash memory comprises of a P-type substrate 100, a deep N-well region 102, a P-well region 104, a stack gate structure 106, a source region 108, a drain region 110, spacers 112, an inter-layer dielectric layer 114, a contact 116 and a conductive line 118. The deep N-well region 102 is embedded within the P-type substrate 100 and the stack gate structure 106 is set up over the P-type substrate 100. The stack gate structure 106 furthermore comprises a tunneling oxide layer 120, a floating gate 122, an inter-gate dielectric layer 124, a control gate 126 and a gate cap layer 128. The source region 108 and the drain region 110 are located within the P-type substrate 100 on each side of the stack gate structure 106. The spacers 112 are attached to the sidewalls of the stack gate structure 106. The P-type well region 104 is within the deep N-well region 102 and extends from the drain region 110 to the area underneath the stack gate structure 106. The inter-layer dielectric layer 114 is above the P-type substrate 100. The contact 116 passes through the inter-layer dielectric layer 114 and the P-type substrate 100 and short-circuits the drain region 110 and the P-type well region 104. The conductive line 118 is positioned over the inter-layer dielectric layer 114 but is electrically connected to the contact 116.
However, as the level of integration of integrated circuits increases and the miniaturization of devices continues, some problems arise. For example, in order to increase the level of integration of a memory device, dimension of each flash memory cell must be reduced. One method of reducing overall memory cell dimension is to shorten the gate length and the separation between data lines. However, reducing the gate length will shorten the channel layer underneath the tunneling oxide layer 120 rendering an electric punch-through between the drain region 110 and the source region 108 more probable. Should such electrical punch-through occur within the device, electrical performance of the memory cell will be seriously compromised. In addition, the photolithographic process used for fabricating the flash memory also has the so-called critical dimension problem, thereby setting a lower limit to the ultimate cell dimension. Furthermore, the drain region 110 and the P-well region 104 are short-circuited together and the P-type well region 104 extends from the drain region 110 into the area underneath the stack gate structure 106. Hence, the P-type well region 104 may not have sufficient thickness in the lateral direction to enclose the drain region (N+ doped). When the memory cell is programmed, the source region receives a voltage of about 6V so that the drain region is at 0V. With this voltage setup, a NPN junction may break down leading to some adverse effect on a nearby flash memory cell. Thus, the ultimate level of integration in a conventional flash memory structure is severely limited.
Accordingly, one object of the present invention is to provide a flash memory device structure and manufacturing process thereof capable of preventing punch-through between a source region (at 6V) and a drain region (at 0V) while performing a programming operation. In the meantime, the level of integration of the memory device is also increased.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a flash memory device structure. The flash memory device structure comprises a first conductive type substrate, a second conductive type first well region, a tunnel dielectric layer, a first floating gate, a second floating gate, an inter-gate dielectric layer, a first control gate, a second control gate, an insulating layer, a spacer, a source region, a drain region, a first conductive type second well region and a first conductive type pocket doping region. The first conductive type substrate has an opening and the second conductive type first well region is embedded within the first conductive type substrate. The tunnel dielectric layer covers the bottom area as well as the sidewalls of the opening. The first floating gate and the second floating gate are attached to the respective tunnel dielectric layer on the sidewalls of the opening. The inter-gate dielectric layer is set up over the first floating gate and the second floating gate. The first control gate and a second control gate are set up over the first conductive type substrate. The first control gate extends to cover the sidewall of the first floating gate and the second control gate extends to cover the sidewall of the second floating gate. The insulating layer is positioned within the space between the first control gate and the second control gate. The spacer is attached to the sidewall of the first control gate and the second control gate respectively. The source region is set up within the first conductive type substrate at the bottom section of the opening. The drain region is set up within the first conductive type substrate just below the spacer. The first conductive type second well region is set up within the second conductive type first well region and that the junction between the first conductive type second well region and the second conductive type first well region is higher than the bottom section of the opening. The first conductive type pocket doping region is set up within the first conductive type substrate adjacent to the opening sidewalls and the first conductive type pocket doping region is connected to the first conductive type second well region and the source region.
In the aforementioned structure, the drain region and the first conductive type second well region are electrically short-circuited together. The electrical short-circuit is achieved through a contact that passes through the junction between the drain region and the first conductive type second well region. Furthermore, the structure further comprises an inter-layer dielectric layer over the first conductive type substrate and a conductive line over the inter-layer dielectric layer. The conductive line is electrically connected to the contact.
In the flash memory device structure of this invention, the gate structure (the tunnel dielectric layer, the floating gate, the inter-gate dielectric layer and the control gate) is set up on the sidewalls of the opening within the first conductive type substrate. Furthermore, the drain region and the source region are set up within the first conductive type substrate near the top section and the bottom section of the opening respectively. The channel region is set up within the P-type substrate (a vertical channel region) on the sidewall of the opening. By controlling depth of the opening, a channel having a desired length can be precisely manufactured. Hence, channel length reduction due to miniaturization is prevented and overall level of integration is increased.
This invention also provides a method of fabricating a flash memory device. First, a first conductive type substrate is provided. The substrate has a second conductive type first well region therein. A liner layer and a mask layer are sequentially formed over the substrate. The mask layer, the liner layer and the substrate are sequentially patterned to form an opening in the substrate. A tunnel dielectric layer is formed over the interior surface of the opening. Thereafter, a first conductive type pocket doping region is formed in the substrate next to the opening sidewalls. A first floating gate and a second floating gate are formed on the sidewalls of the opening and then a source region is formed at the bottom section of the opening. An inter-gate dielectric layer is formed over the interior surface of the opening. A first control gate and a second control gate are formed on the sidewalls of the opening. The first control gate extends to cover the sidewall of the first floating gate and the second control gate extends to cover the sidewall of the second floating gate. Next, the mask layer and the liner layer are removed and then a drain region is formed within the substrate. A first conductive type second well region is formed within the second conductive type first well region. The junction between the first conductive type second well region and the second conductive type first well region is at a higher level than the bottom section of the opening. An insulating layer is formed in the space between the first control gate and the second control gate. First spacers are formed on the sidewalls of the first control gate and the second control gate. After forming an inter-layer dielectric layer over the substrate, a contact is formed within the inter-layer dielectric layer. The contact forms a short circuit connection between the drain region and the first conductive type second well region. Finally, a conductive line is formed over the inter-layer dielectric layer so that the conductive line and the contact are electrically connected.
In the aforementioned method of fabricating the flash memory device, the step of forming the first floating gate and the second floating gate adjacent to the sidewalls of the opening is carried out before forming a first conductive layer that fills the opening. Thereafter, a portion of the first conductive layer is removed so that the upper surface of the first conductive layer is at a level slightly lower than the upper surface of the substrate and then second spacers are formed on the sidewalls of the mask layer. Using the mask layer and the second spacers as a mask, part of the first conductive layer is removed to form the first floating gate and the second floating gate. Finally, the second spacers are removed.
In the aforementioned method of fabricating the flash memory device, the step of forming the first control gate and the second control gate adjacent to the sidewalls of the opening is carried out before forming a second conductive layer that fills the opening. Thereafter, a portion of the second conductive layer is removed so that the upper surface of the second conductive layer is at a level lower than the upper surface of the mask layer but higher than the floating gate. Third spacers are formed on the sidewalls of the mask layer. Using the mask layer and the third spacers as a mask, part of the second conductive layer is removed to form the first control gate and the second control gate. Finally, the third spacers are removed.
The gate structure (including the tunnel dielectric layer, the floating gate, the inter-gate dielectric layer and the control gate) of this invention is formed inside the substrate adjacent to the sidewalls of the opening. In addition, the drain region and the source region are formed in the substrate around the top section and the bottom section of the opening respectively. The channel region is formed within the substrate parallel to the sidewalls of the opening (a perpendicular channel region). By controlling depth of the opening, a channel having a desired length can be precisely manufactured. Hence, channel length reduction due to miniaturization is prevented and overall level of integration is increased.
Furthermore, the floating gates and the control gates are formed by forming spacers over the mask layer and then etching the conductive layer using the spacers and mask layer as an etching mask. Since the fabrication process does not require photolithographic technique, process window is increased and process cost is reduced.
Because the entire gate structure has a vertical orientation, lateral NPN breakdown is prevented when the P-type well region is formed. In addition, unlike conventional BiNOR gate memory cell that requires good NPN isolation and hence demands a lateral drive-in for the P-type well region to increase the NPN range, no lateral drive-in is required in this invention. In other words, deterioration of quality at the interface between the inter-gate dielectric layer (oxide/nitride/oxide ONO) and the tunneling oxide layer due to thermal treatment can be avoided.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.